High precision overlay and registration metrology for the semiconductor industry

Chips have a multilayered architecture. Each layer is put on top of the previous layer in a lithographic process. Controlling the pattern placement from layer to layer is crucial for producing working computer chips reliably. Misplacements of the structures in each layer will result in faulty electric connections between the layers, and therefore result in defective chips. A precise control of this pattern to pattern (or layer to layer) alignment is necessary.

As the semiconductor industry continues to reduce the size of the structures on the chips, requirements for overlay and registration control are getting tighter. This requires increasingly precise overlay metrology (the measurement of pattern to pattern displacement between layers using either specific markers or device structures) as well as registration metrology (the measurement of the pattern position in respect to an absolute grid). However, current metrology solutions have been pushed to their limits. In order to continue the quest for smaller and smaller structures on computer chips, new methods for overlay and registration metrology are needed.

Such a new method should allow an overlay or registration metrology precision much better 1 nm at a throughput larger than 100 wafer per hour for 300-mm wafer. It should work with device structures instead of metrology targets in wafer scribe lines between dies.

To date, mainly three techniques are used to perform such measurements:

• Optical imaging
• Optical scatterometry
• Scanning electron microscopy

However, each of these techniques has significant limitations. Hence, a new method is needed which overcomes the limitations of the established techniques.